Special Panel: The Silicon/Packaging Technology Development to Enable the Next Generation of AI
Distinguished panelists:
Dr Scott Sikorski, IBM VP Business Development, Chiplet and Advanced Packaging
Mr. David McCann, Sr VP, Chief of Staff, Business Unit, Amkor Technology
James G. Dwyer Professor Ganesh Subbarayan, Director of Institute of Advanced System Integration and Packaging, Purdue University
Distinguished Professor Bahgat Sammakia, 绿帽社, VP of Research
Moderators:
Dr Michael W. Condry, Chair of IEEE World Technical Summit, CEO Condry Investment & Future Technology Consultant,
and Retiree CTO Intel Global Ecosystem Development
Dr Gamal Refai-Ahmed, AMD Sr Fellow and Chief Thermo-Mechanical Engineer
Abstract:
The 35th Annual Electronics Packaging Symposium and IEEE Industrial Engagement Committee are cohosting a special panel on "Silicon/Packaging Technology Development to Enable the Next Generation of AI," where distinguished executive leaders from industry and academia will explore the forefront of advancements revolutionizing AI hardware. This panel will reveal an exciting deep dive into the latest silicon and packaging innovations, examining how these technologies are transforming AI performance and efficiency. The expert panelists will unravel the complexities of advanced packaging techniques like 2.5D and 3D stacking, highlighting their critical role in overcoming challenges related to heat dissipation and signal integrity. Discover the importance of heterogeneous integration, the cutting-edge thermal management solutions, and the evolving role of materials science in semiconductor packaging. Engage with insights on how the industry is addressing higher interconnect density demands, the potential of silicon photonics, and the strategies balancing performance, power consumption, and cost in AI chip packaging. Additionally, The panel will explore the implications of a potential advancements, the role of machine learning in packaging optimization, and the significance of academia-industry collaboration in pushing technological boundaries. This panel is set to ignite audience curiosity and provide a comprehensive overview of the emerging technologies poised to disrupt the AI hardware landscape in the coming years. Don't miss this opportunity to gain invaluable knowledge and foresight from the leaders driving the future of AI technology.
Workshop: 鈥淢aterials and Metrology Needs for Advanced Semiconductor Packaging Strategies鈥
Chair: Christopher Soles (NIST)
Abstract:
The drive towards heterogenous integration in the semiconductor industry is placing increasingly stringent demands on the materials that are used in their packaging processes. These packaging materials are often polymers that go through a curing reaction from liquid or semi-solid precursor into the final rigid packaging resin. While issues related to cure shrinkage and coefficient of thermal expansion (CTE) mismatch have always been present, they are becoming more problematic as packages become more complex and the silicon dies become thin and flexible. Cure induced and CTE mismatch stresses lead to significant warpage of the package. These problems are exacerbated as packaging schemes transition from simple 2D to more complicated 3D strategies where the packaging materials must be integrated into increasingly complicated and fragile structures with reduced dimensions. The packaging material must have both structural integrity and function as a high frequency dielectric. These properties are adversely affected by the hygrothermal stressors that semiconductor devices experience. The development of new packaging materials requires a detailed understanding of how their critical properties respond to the different environments and conditions. Measurements that connect material properties as a function of their processing conditions and environmental stressors to their performance in packaging applications are critically needed. Such measurements will be critical to the development of next generation packaging materials that are optimized for performance. The focus of this NIST sponsored symposium is twofold. We will discuss the measurement challenges of the polymeric resins that are ubiquitous in semiconductor packaging. We will also discuss the formulation of non-proprietary, open-source model packaging resins as a platform to address these challenges and generate knowledge for the community. We envision this to be a vehicle that will lead standard test methods, reference materials, and materials databases to help develop the next generation of packaging materials.